By Hendrik van der Ploeg

This ebook analyses assorted A/D-converter architectures with an emphasis at the greatest available strength potency. It additionally offers an obtainable assessment of the state-of-the artwork in calibration thoughts for Nyquist A/D converters. The calibration thoughts provided are acceptable to different analog-to-digital structures, equivalent to these utilized in built-in receivers. they permit implementation with out introducing a pace or strength penalty.

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However, since the pre-amplifier array is not infinite in practice, the RR21 ratio cannot be reduced infinitely. This effect changes the position of the zero-crossings of the pre-amplifiers at both ends of the array. The positions of the zero-crossings can be restored by changing the reference voltages such that the zero-crossings after averaging are at their wanted position [14]. However, unequally spaced reference voltages are undesirable for matching. A more accurate compensation is to apply out-of-range circuitry, such that the zero-crossings of the in-range pre-amplifiers remain at their wanted position.

The minimum required capacitance from both the noise and the matching requirements are quadratically dependent on the required accuracy, while the total capacitance is determined by the maximum of the capacitance from the noise or matching requirement. This maximum capacitance needs to be charged with the respective signal with sufficient accuracy within a certain time period, which is a measure for the power consumption. 6 Conclusions 19 dependent. This makes it possible to compare the power consumption of different A/D converter architectures, as discussed in chapter 3.

This is continued until all stages have performed their conversion. All digital output values are combined to generate the digital output code. Due to the pipelining concept (caused by the inserted SHAs) the first stage can start sampling a new analog input signal while the second stage processes the previous sample. The speed of the conversion is therefore determined by the speed of a single stage. The drawback of this, however, is a larger latency. 23 shows the case for one bit per stage, although more configurations are possible, such as one and a half bits per stage to resolve A/D converter errors [29] or a first stage with three bits and the remaining stages with one and a half bits per stage [30].

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