By Arthur H.M. van Roermund, Herman Casier, Michiel Steyaert

Analog Circuit layout includes in overall 18 tutorials. They replicate the contributions of 6 specialists in all the 3 fields coated by means of the 3 chapters pointed out within the subtitle, as offered on the fifteenth workshop on Advances in Analog Circuit layout (AACD) held in Maastricht, April 2006.

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Extra info for Analog Circuit Design: High-Speed A-D Converters, Automotive Electronics and Ultra-Low Power Wireless

Example text

A Digital-toAnalog converter (DAC) produces an intermediate voltage that is compared to the sampled (and held) voltage. If these two voltages are equal, obviously the digital code at the DAC input corresponds to the input voltage. We can try several algorithms to find the appropriate input code and the binary SA-algorithm is a very popular one. Fig. 2 shows a widely used implementation. It is known as charge-redistribution ADC [1]. During the first phase the switch Sc is closed and the switches SMSB to SLSB are set to “input voltage”.

This primarily corrects the minor third harmonic distortion created in the V/I stages in front of each current-mode ADC. All of the calibration values must be calculated by software external to the ADC; we use the general-purpose CPU already present in an oscilloscope. However, once calibrated, the chip performs all the corrections except the optional lookup table in hardware in real time. It has already been described how the use of calibration allows the use of less-accurate, and thus, smaller and lower-power circuits.

Simplified Schematic of the Current-Mode Amplifier in the Pipeline. When designed to meet the SNR needs of an 8-bit ADC, we had a small, low-power stage with very poor gain accuracy, far, far short of being able to achieve the required 8-bit gain accuracy in the first pipeline stage. We introduced redundancy with a reduced-radix architecture, resolving 1 bit per stage. 00. 6 to guarantee high yields with a large number of pipelines on a die. This in turn called for 12 pipeline stages to reach a resolution of 256 levels.

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